Failure and Degradation Analysis of Commercial 1.2-kV SiC Trench MOSFETs Under Repetitive Short-Circuit Stress

This study offers an in-depth analysis of failure mechanisms and degradation patterns in the state-of-the-art commercial 1.2-kV SiC trench MOSFETs subjected to repetitive short-circuit (RSC) stress. Two commercial trench MOSFETs, specifically the reinforced double-trench MOSFET (RDT-MOS) and asymmetric-trench MOSFET (AT-MOS), were tested at 50% of the maximum single short-circuit (SC) energy, with a drain-source voltage of 800 V. The failure mechanisms were identified through the analysis of leakage current paths, primarily involving thermally induced fractures in the dielectric layer and trench failures caused by elevated temperatures. Unlike single SC tests, where failure is primarily driven by thermal runaway, failure under RSC stress is attributed to cracking of the dielectric layer due to sustained thermal and mechanical stress. In addition, RDT-MOS experienced trench failures due to elevated junction temperature concentrated at the trench corners. Degradation during RSC was observed in both the threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}\text {)}$ </tex-math></inline-formula> and subthreshold swing (SS). Both devices exhibited bidirectional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> shifts, attributed to electrons trapping and holes injection at the interface, while RDT-MOS showed a pronounced increase in SS, indicating the generation of new interface traps under RSC stress.