A Noise Shaping SAR ADC with kT/C Noise Cancellation and Mismatch Error Shaping

The resolution of SAR ADCs is primarily limited by sampling noise, DAC mismatch, and comparator noise. This work presents a noise-shaping SAR ADC design that addresses all these error sources. Sampling noise is mitigated using a kT/C noise cancellation technique combined with resampling. DAC mismatch is managed through data-weighted averaging (DWA) and mismatch error shaping (MES), while comparator noise is reduced using a second-order passive noise-shaping (NS) technique. Designed in a 28nm CMOS process, the ADC achieves 86.8 dB SNDR across a 2.8 MHz bandwidth with a power consumption of 3.8 mW.

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Publication Details

Published
2024-10-25
DOI
https://doi.org/10.1109/icta64028.2024.10860317
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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article

A Noise Shaping SAR ADC with kT/C Noise Cancellation and Mismatch Error Shaping

Shiheng Yang, Bing Du, Zhenbing Li, Jiaxin Liu et al.
Analog and Mixed-Signal Circuit Design
article

A Noise Shaping SAR ADC with kT/C Noise Cancellation and Mismatch Error Shaping

Shiheng Yang, Bing Du, Zhenbing Li, Jiaxin Liu, Tiange Yi
article en

Abstract

The resolution of SAR ADCs is primarily limited by sampling noise, DAC mismatch, and comparator noise. This work presents a noise-shaping SAR ADC design that addresses all these error sources. Sampling noise is mitigated using a kT/C noise cancellation technique combined with resampling. DAC mismatch is managed through data-weighted averaging (DWA) and mismatch error shaping (MES), while comparator noise is reduced using a second-order passive noise-shaping (NS) technique. Designed in a 28nm CMOS process, the ADC achieves 86.8 dB SNDR across a 2.8 MHz bandwidth with a power consumption of 3.8 mW.

University of Electronic Science and Technology of China (CN)
Openalex Percentile: Top 76%
Analog and Mixed-Signal Circuit Design
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