A 470 μW and 875 fps ThroughputJPEG-LS Accelerator in 65nm CMOS
This work presents a low power, high-throughput JPEG-LS accelerator ASIC featuring an 8-stage pipeline architecture and dual-mode computation reuse technology. The chip is fabricated in 65 nm CMOS and occupies $0.71 \ \text{mm}^{2}$ achieving $470 \ \mu \text{W}$ power consumption at 0.8 V supply. With the maximum performance test, this accelerator can achieve a maximum processing speed of 875 fps at a $400 \times 400$ image resolution owing to its 8 -stage pipeline architecture.
Authors
- Nan Wu (ORCID: https://orcid.org/0000-0002-1416-8862)
- Yaoyu Li (ORCID: https://orcid.org/0000-0002-6621-1308)
- Siqi Wang (ORCID: https://orcid.org/0009-0006-9675-7973)
- Hanjun Jiang (ORCID: https://orcid.org/0000-0003-4911-0748)
- Yanshu Guo (ORCID: https://orcid.org/0000-0002-5800-8799)
- Zhihua Wang (ORCID: https://orcid.org/0000-0001-6567-0759)
- Tian Tian (ORCID: https://orcid.org/0000-0003-0634-0455)
Institutions
- Fudan University (CN)
- Tsinghua University (CN)
Publication Details
- Published
- 2024-10-25
- DOI
- https://doi.org/10.1109/icta64028.2024.10860422
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Research and Development