An FVF-LDO with Differential EA and Push-Pull Super Source Follower for Fast Transient Response

This article presents a fully integrated flipped voltage follower (FVF) based low-dropout (LDO) regulator with enhanced transient response for noise-sensitive circuits. Focusing on shorter overshoot response and recovery time, a dual-loop FVF LDO with differential error amplifier (EA) and a push-pull super source follower (PPSSF) is proposed. This work, designed in a 65 nm CMOS process, with 1.2 V input and 1 V output, exhibits a quiescent current ($\text{I}_{\text{Q}}$) of $110 \ \mu \text{A}$. The load current ILOAD ranges from 0 to 20 mA. The circuit achieves 1 ns response time and 122 ns recovery time for both voltage overshoot and undershoot. Furthermore, with 50 dB of DC gain, the LDO reaches a low-frequency power supply rejection (PSR) of -50 dB and the worst full-spectrum PSR of −5.6 dB at 20 mA ILOAD with a 300 pF on-chip capacitor.

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Publication Details

Published
2024-10-25
DOI
https://doi.org/10.1109/icta64028.2024.10860401
Citations
1
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.21

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article

An FVF-LDO with Differential EA and Push-Pull Super Source Follower for Fast Transient Response

Jun Yin, R.S. Chen, Yan Lü, Xiangyu Mao
1 citations
Radio Frequency Integrated Circuit Design
0.21
article

An FVF-LDO with Differential EA and Push-Pull Super Source Follower for Fast Transient Response

Jun Yin, R.S. Chen, Yan Lü, Xiangyu Mao
article en
1 citations

Abstract

This article presents a fully integrated flipped voltage follower (FVF) based low-dropout (LDO) regulator with enhanced transient response for noise-sensitive circuits. Focusing on shorter overshoot response and recovery time, a dual-loop FVF LDO with differential error amplifier (EA) and a push-pull super source follower (PPSSF) is proposed. This work, designed in a 65 nm CMOS process, with 1.2 V input and 1 V output, exhibits a quiescent current ($\text{I}_{\text{Q}}$) of $110 \ \mu \text{A}$. The load current ILOAD ranges from 0 to 20 mA. The circuit achieves 1 ns response time and 122 ns recovery time for both voltage overshoot and undershoot. Furthermore, with 50 dB of DC gain, the LDO reaches a low-frequency power supply rejection (PSR) of -50 dB and the worst full-spectrum PSR of −5.6 dB at 20 mA ILOAD with a 300 pF on-chip capacitor.

University of Macau (MO), Tsinghua University (CN)
National Natural Science Foundation of China, Technology Development
Openalex Percentile: Top 44%
Radio Frequency Integrated Circuit Design
0.21
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An FVF-LDO with Differential EA and Push-Pull Super Source Follower for Fast Transient Response — Jun Yin, R.S. Chen, et al. · (2024) | TGRS Research Map | TGRS