Design Technology Co-Optimization for Memristor Self-Write Termination Circuits

The variations of memristors can cause a degradation of computational precision in the compute-in-memory (CIM), consistently impeding the deployment of CIM applications. The random growth of conductive filaments is an intrinsic property, so that the variation is difficult to overcome through fabrications. Nonetheless, this study offers a viable approach to mitigating variation through the design of circuit and technology co-optimization (DTCO). By integrating the HfOx/AlOy superlattice-like device fabrication with a feedback circuit, this work has achieved the precise self-write termination of the memristor resistance. The results of test demonstrate that the superlattice-like memristors exhibit favorable gradual resistance change, which makes the feedback circuitry adjust the resistance in time. In comparison to the write-verification, this self-write termination has minimized variations and boosted endurance effectively.