A 92.9dB-SNDR 178.2dB-FoMs SAR ADC with kT/C noise cancellation and FIA

When designing high resolution ADCs, SAR ADCs face limitations due to sampling $\mathrm{kT} / \mathrm{C}$ noise. The input capacitor size has to be very large. This poses burdens for ADC driver, leading to huge power/area costs and design complexity. We introduce a SAR ADC with noise cancellation and FIA, a fully dynamic amplifier with high power efficiency. A 17-bit SAR ADC was fabricated using a 28 nm CMOS process with a 0.35 MHz bandwidth, achieving 92.9dB SNDR and 178.2dB FoMs in simulation.