Re-CATA: Real-Time and Flexible Accelerator Design Framework for On-Device Codec Avatars
Real-time Codec Avatars, which employ deep generative models for 3-D reconstruction of human features, are crucial for immersive telepresence in augmented reality and virtual reality (AR/VR) environments. However, deploying these avatars in real-time on AR/VR headsets is challenging due to the inability of existing devices to achieve satisfying performance within stringent hardware resource constraints. To address these challenges, we introduce Re-CATA, an innovative full-stack and flexible Codec Avatar accelerator design framework. Re-CATA is designed to deliver real-time throughput (greater than 120 FPS) for the complete Codec Avatar processing pipeline within an edge-level power budget of 5 W under FPGA prototyping. Our approach begins by abstracting the operation mapping and scheduling challenges inherent in Codec Avatars, which require both centralized and distributed processing to handle dynamically changing workloads. We propose a novel hardware resource and workload partitioning scheme optimized for these fluctuating demands. To complement this, we introduce an agile runtime scheduling system for efficient workload reallocation among computing units as needed, recognizing the limitations of static partitioning in rapidly evolving workload scenarios. Furthermore, our micro-architecture design incorporates unified computing modules and efficient hardware peripherals, enabling seamless workload balancing across the Codec Avatar processing pipeline. We evaluate the Re-CATA accelerators via on-board FPGA prototyping, comparing them to various baselines, including commercial AR/VR system-on-chips and academic accelerators. This evaluation demonstrates a maximum speedup of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.95\times $ </tex-math></inline-formula> under similar settings.
Authors
- H. Ekin Sumbul (ORCID: https://orcid.org/0000-0001-6812-8033)
- Yingyan Lin (ORCID: https://orcid.org/0000-0001-5946-203X)
- Cheng Wan (ORCID: https://orcid.org/0000-0002-2295-3481)
- Yonggan Fu (ORCID: https://orcid.org/0000-0002-7483-2921)
- Syed Shakib Sarwar (ORCID: https://orcid.org/0000-0002-0086-1076)
- Yuecheng Li (ORCID: https://orcid.org/0009-0008-3447-6214)
- Haoran You
- Yongan Zhang (ORCID: https://orcid.org/0000-0001-7919-049X)
Institutions
- Georgia Institute of Technology (US)
Publication Details
- Journal
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Published
- 2025-02-06
- DOI
- https://doi.org/10.1109/tcad.2025.3539600
- Primary Topic
- Distributed and Parallel Computing Systems
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Semiconductor Research Corporation