A 25-GHz PLL Achieving 8-ns Phase-Shifting Time With Double-Path Modulation Scheme

This article presents a reference phase-shifting architecture (PSA) based on a phase-locked loop (PLL) and a digital-to-time converter (DTC). The double-path phase modulation scheme (DPMS) is proposed to accelerate the settling time of the reference PSA. Off-chip calibration is added to mitigate the effects of nonlinearity in the DPMS process. Additionally, a DTC with improved retiming is proposed to reduce phase-shifting errors. The reference PSA with the DPMS is designed and fabricated in a commercial 22-nm CMOS technology. It occupies 0.048-mm2 active area and 12.8-mW dc power consumption. It achieves a 360° phase tuning range with a resolution of 1.26° at 24.75 GHz. The rms and peak phase errors are 1.38° and 2.6°, respectively. With the proposed DPMS, the settling time of reference PSA is significantly reduced from more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\mu $ </tex-math></inline-formula> s to less than 10 ns. Moreover, the PLL with DTC features a phase noise of −112.1 dBc/Hz at 1-MHz offset from 24.75 GHz and a 79.7-fs jitter integrated from 10 kHz to 30 MHz with 250-MHz reference clock. The figure of merits (FoMs) of jitter versus power for the proposed PLL with and without DTC are −250.9 and −251.4 dB, respectively.