A pipelined ADC calibration technique based on time-delay neural network with ant colony optimization

This paper presents a pipelined analog-to-digital converters (ADCs) calibration method that integrates ant colony optimization (ACO) algorithm with time-delay neural network (TDNN). The proposed method uses TDNNs to calibrate the integral nonlinearity error of the ADC, and leverages the global search capability of ACO to optimize the time-delay feature dimensions and the initial parameter configuration of the neural network. This approach improves the calibration performance, reduces the model size, and avoids converging to local optima. The calibration method was evaluated using a commercial 14-bit, 1 Gsps pipelined ADC chip. The results show that this method improves the SNDR from 63.80 dB to 79.31 dB, SFDR from 82.50 dB to 95.65 dB, and ENOB from 10.31 bits to 12.88 bits. Additionally, this method identifies the optimal time-delay feature combination with a 100% probability of global optimal calibration performance.