Carry Tree Adders on FPGA's Design and its Implementation

Binary adders are vital parts for designing digital circuits. Traditional ripple carry adders were simple, but they have considerable delays, especially at bigger bit widths. To address this issue, carry tree adders, also known as parallel prefix adders, have developed as powerful replacements. This work focuses on constructing a comparison of several carry tree adder designs (Kogge-Stone, Brent Kung, and Han Carlson) to ripple carry and carry lookahead adders. The research seeks to determine the most practical adder design for certain applications by comparing latency, area, and effectiveness across different bit widths using a Spartan 3E FPGA.