Design of All Digital Phase Locked Loop for Binary Frequency Shift Keying Modulation

In the rapidly advancing field of digital communication, the All Digital Phase Locked Loop (ADPLL) serves as a vital component for achieving precise clock synchronization. An ADPLL (All-Digital Phase-Locked Loop) is widely used in digital communication systems for clock generation, synchronization, and modulation, providing precise frequency control essential for high-speed data transmission and signal integrity. This paper presents the design and implementation of an ADPLL, where all four essential blocks—Phase Frequency Detector (PFD), Proportional-Integral (PI) Controller, 5-Stage Ring Oscillator, and Divide-by-N Counter in the feedback loop are implemented digitally. The ADPLL is designed with a center frequency of 100 MHz and demonstrates a lock range from 94 MHz to 106 MHz, showcasing its capability to maintain phase and frequency synchronization across a specified range. The described ADPLL finds its application in digital communication systems, particularly in Binary Frequency Shift Keying (BFSK) modulation. The entire design is realized using Verilog, and comprehensive testbenches were developed to simulate and verify the functionality of the system. The Vivado Xilinx tool was employed for simulation, enabling detailed analysis of the waveform outputs and confirming the ADPLL's effectiveness in digital communication scenarios.