Low-Power SRAM Memory using Sleepy-Stack Hybrid Power Gating Technique

Nowadays, with everything being digital, memory is an essential part of any integrated device. It makes a substantial contribution to the circuit power overall as well. The growing demand for portable devices is driving chip manufacturers’ interest in nanotechnology. Static random access memory (SRAM) components make up the majority of portable devices, and their power consumption is inversely correlated with the technology used. This trade-off has led to the development of several leakage reduction techniques. We compare the different strategies (sleep, stack, keeper, and lector) in this work and propose power gating techniques to enhance the reduction of leakage power. Simulations have been performed on Tanner.