An 800MS/s Continuous-Time Pipeline ADC with Switchable FLASH and RDAC for Background Calibration

This paper presents a continuous-time pipeline ADC with background calibration. The calibration is based on split structure. A switchable FLASH and RDAC is proposed to achieve the shift of residue modes compatible with PN injection for continuous input. Additionally, the taps of the digital reconstruction FIR are iterated by LMS. An 800MS/s 100MHz BW two-stage continuous-time pipeline ADC using the proposed calibration method is implemented in a 65 nm CMOS technology, achieving SNDR of 67.6dB with 13.09MHz -2.5dBFS input. There is only 1-dB deterioration in SNDR compared to the classical foreground calibration with noisemin algorithm. However, this method can achieve background calibration with much lower hardware cost.