An FPGA-based QDI Asynchronous Circuits Design Methodology

Quasi delay insensitive (QDI) circuits, as a type of asynchronous circuits, have unique advantages such as high robustness, low power consumption, and event driven, so they have the potential to be applied in fields such as Network-on-Chip (NoC). However, due to the lack of supporting EDA tools, designing QDI circuits is difficult, resulting in limited application. This article proposes a systematic FPGA-based QDI circuit design methodology based on existing EDA tools, and designs a QDI router according to the proposed methodology. The designed QDI router reduces power consumption by 52.1% and latency by 19.7% compared to synchronous router with similar structure.