Missing/Extra Via Check Algorithm for Advanced VLSI Analog Designs

This paper presents an original algorithm and the application of a Via Check script implemented in the PVS/Pegasus Verification System Tool (Cadence). The algorithm was written in the physical verification language. Via Check is mainly looking for places in the layout where connections (vias) between metals within the same net are missing or could be reinforced. The designed tool was equipped with special user interface graphics to filter the obtained results for more convenient use. It was successfully used in many projects involving advanced submicron technologies like cmos65lp, cmos40lp, stios40nm, stios28nm, 16ff, and 12ff for almost two years. Its application supported by examples of the results from ongoing projects is also included in this publication.