Design and Circuit-Level Assessment of Memristor-NMOS for Low-Power Applications

This manuscript presents an essential overview of the implementation of memristor-based logic circuits. Different memristor models such as Linear Drift, Simmons Tunnel, Yakopcic, N on-Linear ion Drift, TEAM, and VTEAM have been taken into consideration and a comparison of results has been done adopting all these models. The logic gates such as NAND, NOT, NOR, AND, OR along with some combinational circuits such as a l-bit comparator, and 2xl multiplexer were designed and implemented using MRL (Memristor Ratioed Logic) in the L TSpice simulation tool. The primary target of this paper is affirming the attributes of memristor at the device level. Here the logic circuits are implemented using Memristor and NMOS devices. All the circuits designed in this paper operate at a supply voltage of lV using HP memristor model. Moreover, the power consumed by the designed circuits has been analyzed and found to be in the order of p W.