An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications
Floating-point (FP) CIM is an attractive technique that achieves high accuracy with considerable energy efficiency, especially for complex artificial intelligence tasks. However, FP-CIM with FP32/FP16/BF16 data format incurs a performance bottleneck due to the large storage requirements and MAC power. The emerging POSIT data format exploits dynamic bit width that adapts to varied data distributions, enabling using a low-bit-width to reach nearly the same accuracy performance as conventional high-bit-width FP (POSIT<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8~{\approx }$ </tex-math></inline-formula> FP16/BF16). Therefore, a POSIT-based CIM exhibits inherent advantages over the traditional FP-CIM. Despite the theoretical superiority, the dynamic property of POSIT introduces huge exponent processing overhead, cell underutilization of the CIM array, and redundant logic toggles in mantissa addition for POSIT-base CIM. This article presents a POSIT-based digital CIM (PD-CIM) macro with three features to tackle the above challenges: 1) a bi-directional regime processing unit (BRPU) simplifies the complicated codec logic to reduce the energy overhead in dynamic exponent processing; 2) a critical-bit pre-compute-and-store (CPCS) CIM utilizes the spare CIM cells caused by the dynamic bit-width of mantissa to improve cell utilization of the CIM array; and 3) a cyclically alternating computing-scheduling unit replaces the bit-wise addition of dynamically aligned mantissas with bit-wise OR to save logic toggles power. Fabricated in a 28 nm CMOS technology, PD-CIM occupies an area of 1.41 mm2. It reaches an 83.23 TFLOPS/W peak energy efficiency at POSIT(8,1) for ImageNet classification on the vision transformer base (ViT-B) model. Compared with the state-of-the-art FP-CIM, PD-CIM reduces energy by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.36{\times }$ </tex-math></inline-formula> and offers <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.51{\times }$ </tex-math></inline-formula> speedup.
Authors
- Zhiheng Yue (ORCID: https://orcid.org/0000-0003-4084-3478)
- Yang Wang (ORCID: https://orcid.org/0000-0002-8293-8881)
- Shaojun Wei (ORCID: https://orcid.org/0000-0001-5117-7920)
- Shouyi Yin (ORCID: https://orcid.org/0000-0003-2309-572X)
- Xiaolong Yang (ORCID: https://orcid.org/0000-0001-6893-0990)
- Yang Hu (ORCID: https://orcid.org/0000-0001-6942-4395)
- Yubin Qin (ORCID: https://orcid.org/0000-0001-5530-5416)
- Ruiqi Guo (ORCID: https://orcid.org/0000-0003-4729-7385)
- Huiming Han
- Zhiren Zhao (ORCID: https://orcid.org/0009-0007-6074-7324)
Institutions
- Tsinghua University (CN)
Publication Details
- Journal
- IEEE Journal of Solid-State Circuits
- Published
- 2025-02-05
- DOI
- https://doi.org/10.1109/jssc.2025.3532654
- Citations
- 3
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 2.19
Funders
- National Natural Science Foundation of China
- Beijing National Research Center For Information Science And Technology
- National Key Research and Development Program of China