A Monolithic 5.7 A/mm² 91% Peak Efficiency Scalable Multistage Modular Switched Capacitor Voltage Regulator for Base Die Vertical Power Delivery in 3D-ICs

The rapid increase of silicon die area and power requirements of modern processors, requires a minimal power delivery footprint. Unlike conventional lateral power delivery (LPD), vertical power delivery (VPD) with high input voltage offers a higher density solution, freeing up the top-side package area for more compute and memory dice, and significantly improving overall energy efficiency. However, the development of high-voltage and high-efficiency voltage regulators (VRs) with low-profile passives has lagged behind these advancements. This article presents a monolithic multistage modular switched capacitor VR (MMSCVR) in 16 nm CMOS for VPD. It features: 1) scalable design in both current and voltage domains; 2) optimal deadtime control with self-timed deadtime generator (STDG); and 3) energy efficient, electrical overstress (EOS) free start-up sequence with multilevel mid-rail voltage generator (MMVG). The proposed solution demonstrates 90.6% peak efficiency and 5.7 A/mm2 peak current density with a 3-to-1 V conversion— <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.9{\times }$ </tex-math></inline-formula> higher than state-of-the-art. The 4-to-1 V variant is the first high-density fully monolithic 4-to-1 V SCVR, achieving <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.8{\times }$ </tex-math></inline-formula> higher current density than any prior art using off-chip capacitors.