Nanotechnology-Enhanced Multipliers: Leveraging FinFET and GnrFET in Advanced Digital Systems

Multipliers find applications in high-performance computing and advanced digital systems, where speed and energy efficiency are crucial. Existing Fin Field Effect Transistor (FET) multipliers face challenges such as high-power consumption and significant propagation delays due to limitations in scaling and increased short-channel effects. These issues hinder performance and efficiency significantly as technology nodes shrink. The proposed Dynamic Path Auto-Configurable Multipliers (DPAM) leverages FET (FinFET) and graphene nanoribbon FET (GnrFET) technologies to enhance speed and reduce power consumption. By incorporating Reconfigurable Booth Encoding (RBE), the multiplier efficiently handles large data values with reduced complexity and increased speed. The Dynamic Path Auto-configuration Adder (DPAA) optimizes the carry propagation paths, improving performance and energy efficiency. Integrating these advanced technologies results in a multiplier with superior characteristics compared to conventional designs. The performance metrics of DPAM include Total Path Delay (TPD) at 44.681 ns, Carry Out Rise Delay (CORD) at 43.180 ps, and Carry Out Fall Delay (COFD) at 40.902 ps, indicating efficient signal propagation. The Sum Rise Delay (SRD) is recorded at 43.190 ns, and the Sum Fall Delay (SFD) is 44.756 ns, showcasing balanced and stable operational delays. These values reflect the system's optimized delay characteristics for high-speed computational tasks.