Charge Trap Cell Inverter Implementation for 10-T SRAM In-Computing Memory AI Operations

This paper presents a novel Charge Trap Cell (CTC) inverter implementation for a 10-transistor Static Random Access Memory (SRAM) architecture, aimed at accelerating the training process of Convolutional Neural Networks (CNNs) by optimizing Multiply and Accumulate (MAC) operations. By performing MAC operations directly within the memory using charge trapping mechanisms, the design enables efficient local data retention, reducing reliance on external data transfers between secondary memory and processor. This approach not only enhances data processing speed but also improves overall computational efficiency, leading to faster CNN training cycles. Although the complete Charge Trap Cell SRAM (CTC-SRAM) architecture is still conceptual, the successful implementation of the CTC inverter provides a strong foundation as it provides 90% similarity to conventional MOSFET inverters, confirming its reliability for scaling it to SRAM.