Neuron Circuit Design and Signal Integrity Analysis of a Large-Scale Memristor-Based Crossbar Array

This article addresses the limitations of standard chips in processing large-scale datasets by leveraging neuromorphic architectures, particularly spike neural networks (SNNs), to simulate the pulsed signals of biological brains for enhanced power efficiency and performance. Initially, we developed a complementary metal-oxide–semiconductor (CMOS) circuit based on the integrate-and-fire (IF) neuron model, which generates spike signals with the spatiotemporal dynamics typical of neurons. This approach provides a novel perspective for neuromorphic chip design. Next, we introduce the partial element equivalent circuit (PEEC) method to establish a unit circuit model for the memristor crossbar array, accounting for all resistance-inductance–capacitance (RLC) parasitic couplings. This model enables precise signal integrity (SI) analysis, offering deeper insights into the signal transmission mechanisms within memristor crossbar arrays and serving as a foundation for optimizing neuromorphic chip performance. Building upon this model, we designed a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$24\times 24$ </tex-math></inline-formula> crossbar array hardware prototype, experimentally validating the reliability and feasibility of the circuit. Finally, we perform SI analysis to demonstrate that the performance of the memristor crossbar array can be enhanced by optimizing the rise time, adjusting the memristor’s resistance state, and adding inductance at the output. These findings provide both a theoretical foundation and a technical pathway for improving the performance of neuromorphic chips in practical applications.