A Fully Integrated GaAs MMIC Asymmetric Doherty Power Amplifier With Enhanced Gain Flatness

A novel fully integrated asymmetric Doherty power amplifier (DPA) with optimized driver is proposed. By adjusting the unequal power divider (UPD) and the bias conditions of two-stage carrier and peak power amplifiers (PPAs), good back-off efficiency (BOE) and gain flatness have been achieved. To validate the proposed concept, a 2.45-GHz asymmetric DPA (ADPA) is fabricated in 2-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) process. Under continuous-wave (CW) measurement, the power amplifier (PA) can provide a saturated output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {SAT}}$ </tex-math></inline-formula>) of 32.3 dBm with a power added efficiency (PAE) of 28% at 2.45 GHz. The measured PAE is higher than 21% at 7-dB power back-off (PBO) levels. Furthermore, under the excitation of 256-quadrature amplitude modulation (QAM) signal, the proposed ADPA achieves a PAE of 22% at an average output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {avg}}$ </tex-math></inline-formula>) of 25.8 dBm with DPD while ensuring that the EVM is better than −32 dB.