FPGA Cluster Based System with Adaptive TMR/DMR for Soft Error Mitigation

In recent years, the probability of soft error occurrence has increased due to the miniaturization of semiconductor devices and reduced operating voltages. FPGAs (Field Programmable Gate Arrays) enable designers to program circuit configurations after manufacturing and have flexibility and high power consumption performance. Thus, FPGAs are used for various purposes. This study has presented a redundant FPGA cluster system with error correction capability and archives more efficient use of devices by switching between TMR and DMR according to the situation. The probability of not correctable errors increases by 1.67, but parallel computation allows for twice as fast computation. We implemented a high-level synthesized circuit and applied the proposed method to an FPGA cluster. This experimentation with the implemented system verified that the proposed system’s reconfiguration from DMR to TMR worked correctly.