Suppression of Dynamic Resistance Degradation in 1200-V GaN-on-Sapphire E-Mode GaN HEMTs by Drain-Side Thin p-GaN Design

Dynamic resistance degradation, which is severely affected by the trapping effect, is a critical challenge for lateral AlGaN/GaN power devices, especially when operating in high-voltage and high-frequency applications. In this brief, an enhancement-mode p-GaN gate HEMT with a drain-side thin p-GaN (DST) structural design is proposed. The DST design can suppress the dynamic resistance degradation by injecting holes from the drain-side p-GaN. Meanwhile, by thinning the p-GaN layer, the on-state current conduction characteristics of the DST-HEMT can be greatly improved. The thinning process of the drain-side p-GaN is carried out simultaneously with the source/drain ohmic contact region etching process, which is well compatible with the existing process platform. By performing circuit-level dynamic resistance testing, GaN-on-sapphire DST-HEMT achieves minimal dynamic resistance degradation under 1200-V <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state bias conditions, which is comparable to the test results in vertical GaN-on-GaN devices. In addition, the dynamic switching capability of the device is also demonstrated. These results reveal the notable potential of GaN-on-sapphire DST-HEMTs for high-voltage and high-power applications.