Multiscale Modeling of Self-Heating-Induced and Deformation-Accelerated Dielectric Traps Impacting Critical Path of Dielectric Breakdown in 5-nm Stacked Nanosheet FET

A multiscale model that determines self-heating effect (SHE)-induced and mechanical deformation-accelerated trap generation and also assesses its impact on dielectric breakdown (BD) in hafnium-oxide (HfO2)/(interfacial)silicon dioxide (SiO2)-based gate-stack in a 5-nm stacked nanosheet field effect transistor (SNFET) has been developed here. Initially, T-CAD thermodynamic (TD) simulation was performed to estimate nonuniform SHE across SNFET under applied SHE bias, which was later supplemented by a multiphysics-based simulation as was executed to extract process (anneal) derived residual stresses from both silicon nanosheets and surrounded dielectric layers. Furthermore, simulated deformation profiles were provided as inputs to an ab initio simulation module, which calculated the spatial variations of defect [neutral oxygen vacancies (NOVs)] formation energies (FEs) either across HfO2 or (interfacial) SiO2 molecules. Updated FEs and local temperatures of dielectrics due to SHE in SNFET were then fed as inputs to a standard thermochemical trap generation model for profiling trap generation rates within the dielectric layers. Later, the critical path (CP) of dielectric BD was assessed by a shortest path search algorithm, which estimated the costs of all probable percolating paths through joining the trap generation sites between gate and nanosheet channels and then organized them as per their precedence for analyzing the critical BD path.