Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis

We propose a novel transistor-level synthesis method to minimize the number of transistors needed to implement a digital circuit. In contrast with traditional standard cell design methods or transistor-level synthesis methods based on single-input “complex” gates or “super” gates, our method considers multioutput clusters as the basic resynthesis unit. Our tool takes any gate-level circuit netlist as input and divides it into several clusters of user-controlled size. For each output of a cluster, a simplified sum of product (SOP) expression is obtained and all such expressions are jointly minimized for the cluster using the MOTO-X multioutput transistor-level synthesis tool. Then, we consider groups of clusters, referred to as “superclusters,” to collectively reduce the overall transistor count. Experimental results indicate average transistor count reductions compared to the ABC synthesis tool of 9.95%, 6.53%, 10.49%, 13.09%, and 9.76% for the ISCAS’85, LGSynth’89, LGSynth’91, EPFL’15 and ITC’99 benchmark suites, respectively. Furthermore, our proposed approach proves to be more efficient than the transistor-mapped binary decision diagram approach, highlighting the potential of our methodology for optimizing integrated circuits at the transistor-level while delivering enhancements in power efficiency and demonstrating varied improvements in delay performance.