Double-Layer-Stacked Silicon Interposer for 2.5-D Packaging of 32 × 32 Micromirror Array Chip

Aimed at packaging our previously developed bulk-silicon-micromachined <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32\times 32$ </tex-math></inline-formula> micromirror array (MMA) chip (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$33\times 34\times 0.4$ </tex-math></inline-formula> mm3 in dimension and 4114 pads) while minimizing coefficient of thermal expansion (CTE) mismatch, this article, for the first time, develops a double-layer-stacked silicon interposer (DLSSI), which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$49.8\times 49.8\times 0.387$ </tex-math></inline-formula> mm3 in dimension and has eight redistribution layers (RDLs). It is realized by fabricating two single-layered silicon interposers (SLSIs) with 175-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m-thickness core layer and four RDLs equally arranged on both sides and then adopting Cu-Sn bonding to integrate them together. Such design improves the thickness and the number of RDLs of silicon interposers; thus, the DLSSI not only has higher structural strength for guaranteeing itself to go intact through packaging process but also has higher routing capability for numerous and complicated electric interconnections. Herein, the total quantity of electrical interconnections in the DLSSI is 8336. A dimension-by-dimension fan-out strategy is proposed, which successfully maps pads of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32\times 32$ </tex-math></inline-formula> MMA chip to their corresponding pads of high voltage ASICs (HV-ASICs) in four RDLs (the remaining four RDLs are for powers, reference voltages, and control signals of the HV-ASICs). The equivalent CTE of the DLSSI is calculated to be 3.5 ppm/°C, and the theoretical warpage of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32\times 32$ </tex-math></inline-formula> MMA chip after the packaging process is calculated to be about <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3~\mu $ </tex-math></inline-formula> m with full-scale finite element analysis (FEA). Besides, the warpage and conductance yield of the DLSSI are measured experimentally. Based on the DLSSI, a vertically integrated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32\times 32$ </tex-math></inline-formula> MMA module that includes a PCB connector, 16 HV-ASICs, and 80 capacitors is developed successfully.