Hybrid Recursive Karatsuba Multiplications on FPGAs

The demand for large integer polynomial multiplications has become increasingly significant in modern cryptographic algorithms. The practical implementation of such multipliers presents a field of research focused on optimizing hardware design concerning space and time complexity. In this letter, the authors propose an efficient polynomial multiplier based on a hybrid recursive Karatsuba multiplication (HRKM) algorithm. The overall performance of the proposed design is evaluated using the area-time-product (ATP) metric. The hardware implementation of the proposed architecture is carried out on a Virtex-7 FPGA device using the Xilinx ISE platform. Hardware implementation results show that the proposed HRKM architecture shows ATP reduction of 67.885%, 70.128%, and 65.869% for 128, 256, and 512 bits, respectively, in comparison to Hybrid Karatsuba (nonrecursive) multiplications.