A 0.07 pJ/b/dB 36-Gb/s PAM-3 Receiver Using Inductor-Reused CTLE and One-Tap Loop-Unrolled DFE in 22-nm CMOS

This paper presents a 36 Gb/s (23.04 GBaud) 3-level pulse amplitude modulation (PAM-3) receiver (RX). The proposed inductor-reused continuous-time linear equalizer (CTLE) uses feedforward and inductive peaking techniques. Additionally, the number of the data slicers is reduced in the PAM-3 receiver with a loop-unrolled decision feedback equalizer (DFE). Furthermore, a baud-rate phase detector (BRPD) is presented. Fabricated in 22-nm CMOS technology, this receiver compensates for a channel loss of 20.5 dB at 11.52 GHz, achieving a bit error rate (BER) of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-12} $ </tex-math></inline-formula> with a pseudo-random ternary sequence (PRTS) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3^{7}\mathbf {-}1$ </tex-math></inline-formula>. The measured clock integrated jitter is 267 fsrms at 720 MHz, and the retimed data exhibits 10.98 pspp jitter. The overall receiver consumes 51.7 mW, with a calculated energy efficiency of 1.44 pJ/b and a figure of merit (FoM) of 0.07 pJ/b/dB.