Analytical Modeling of Temperature-Resilient Cylindrical Gate Engineered Ferroelectric Nanowire Field-Effect Transistor

This study introduces an analytical framework for assessing how temperature affects gate-induced drain leakages (GIDL) in a cylindrical gate engineered ferroelectric nanowire field-effect transistor (CGEF-NW-FET). Temperature stands out as a pivotal factor impacting device reliability. The study solves 2-D Poisson’s equation with appropriate boundary conditions to develop and analyze surface potential, electric field <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} _{z}$ </tex-math></inline-formula>, and GIDL current. It investigates how temperature influences potential, hole concentration, and hole velocity through contour plots, and comprehensively examines conduction band energy (CBE) and valence band energy (VBE). Furthermore, it conducts a comparative analysis between the proposed device and a conventional device to understand temperature’s impact on various parameters. This research suggests that the device shows promise for applications where resilience to temperature fluctuations is crucial.