Design and Implementation of D-Flip Flop For Computation in Memory

As the number of data-intensive applications has grown, the traditional Von Neumann computer architecture has become constrained. To address the issue, the new technology platform "computation-in-memory" was established. A new design of the D Flip flop implemented in a memory array employing 8T static random-access memory (SRAM) and latch-type sense amplifier is proposed in this study. To implement the D Flip Flop, this design employs a master-slave multiplexer (MUX) architecture. It has a setup time of 94.887ps and a hold time of 97.22ps.