Triple Source Thirteen Level Inverter

Multilevel inverters are attracting the attention of investigators concerning high-power and mediumpower applications. Interestingly, an arrangement with a couple of devices is popular in an attempt to enhance efficacy and durability. This work suggests a Triple Source Thirteen Level Inverter based on minimal device count. By integrating three voltage sources with eight semiconductor devices, the proposed design develops thirteen levels. Gating signals are created using the Phase Disposition Pulse Width Modulation (PDPWM) technique. To compute efficiency along with losses PLECS software is used. The successful configuration implementation is investigated using MATLAB/Simulink under various parametric conditions. The proposed topology is tested using Hardware-In-the-Loop (HIL) experiments to validate its feasibility.