An Efficient Performance-Driven Analog IC Placement Optimizer Via Extremely Randomized Tree-Based Post-Layout Performance Regressors

This paper presents a performance-driven (PD) analog integrated circuit (IC) placement generator highly integrated with off-the-shelf tools, e.g., simulator, layout-versus-schematic and extractor, that promotes an exhaustive simulation-based synthesis. However, to bypass the timeconsuming extractions and simulations, novel post-layout performance regressors based on different highly accurate machine learning (ML) techniques are developed. The data used to train them can be directly and conveniently acquired from previous precise post-placement simulations. Experimental results show that a set of performance regressors based on extremely randomized trees (ERTs) operating on compressed design spaces allow to speed-up synthesis more than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$20 \times$</tex>, which represents a step forward towards an efficient fully automatic PD analog IC design flow.