A Template-Based Methodology for Efficient DNNs Inference on FPGA Devices With HW-SW Co-Design

Convolutional neural networks (CNNs) are the epitome of artificial intelligence (AI)-based applications. The computationally intensive convolution operation is the core of the entire architecture. Acceleration of CNN-based applications requires several algorithmic level manipulations and optimization for resource-constrained devices. In this work, we have proposed a template-based methodology for CNN acceleration on field programmable gate arrays (FPGA) hardware by designing reusable cores for individual layers like convolution, pooling, and dense layers. We explored various optimization techniques to achieve the best-hardware-designing strategy with data reuse and design space exploration. We have verified our methodology for LeNet-5 with kernel <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times 5$ </tex-math></inline-formula> and a custom CNN with kernel <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times 3$ </tex-math></inline-formula> for classification. The hardware-system design was validated on FPGA Xilinx XC7Z020 FPGA. Our proposed methodology achieves 2.9 GOPS/s performance outperforming existing implementation by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.28\times $ </tex-math></inline-formula>.