A non-volatile and radiation-hardened SRAM based on fourteen transistors and two perpendicular anisotropy magnetic tunnel junctions

As a high-speed memory, the static random-access memory (SRAM) has been widely used and well investigated. However, with the advanced manufactory technology develops and the critical dimension of transistor scales rapidly, SRAM has confronted with many challenges, such as the high-power consumption and the robustness issue, which impede the application of SRAM in advanced electronic devices. Here, by integrating two perpendicular anisotropy magnetic tunnel junctions (p-MTJs) to the conventional SRAM and reinforcing the CMOS circuits, a non-volatile and radiation hardened SRAM (NVRH-SRAM) design based on 14 transistors (14T) and 2 p-MTJs has been implemented. This MTJ-based NVRH-SRAM is primarily single event upset (SEU) tolerant and is a promising candidate for low power circuits, aerospace devices, and other high-speed memory applications. • A non-volatile and radiation hardened SRAM (NVRH-SRAM) design has been implemented. • NVRH-SRAM composed of 6T SRAM, two MTJs and the reinforced CMOS peripheral circuits. • The MTJ/CMOS simulations demonstrated SEU immunity and nonvolatility of NVRH-SRAM. • NVRH-SRAM is a potential candidate for low-power memory and aerospace applications.