Analysis of Energy Efficient Differential Fault Tolerant Adders with Minimized Nonlinearities

In this paper, two 1-bit Differential fault tolerant Full Adder circuits (1b-FA)proposed focusing on reducing nonlinearities to improve performance and reliability in modern electronic systems, using Carbon Nano FETs (CNFETs).Transmission gate logic and pass transistor logic is being used in proposed adders to improve energy and fault tolerant characteristics of Full Adder. Fault detection and fault correction mechanisms are proposed in outputs of 1-bit differential full adder. The proposed fault detection can detect only single error and proposed error correction can correct it. By using Cadence Virtuoso tool, the proposed design is simulated with 32 nm CNFET technology at a supply voltage (VDD) of + 0.9V. The performance of proposed full adder designs has been comparedwithexisting designs in terms of power, delay and power-delay product (PDP). The proposed full adders supply voltage is being varied over a range and can observe the characteristics of full adder with respect to variations in supply voltage (VDD).