2nd Generation 3D V-Cache TM Enablement

Here we present AMD’s 2nd generation 3D V-Cache TM technology and package level results. Key highlights are: 1. Use of face to back (F2B) stacking of 7 nm node cache memory chiplet (SRAM chiplet) on 5 nm node logic chiplet (“Zen 4” compute chiplet). 2. Bond pad via (BPV) landing on top Aluminum pad (AP) instead of top metal layer With the slowdown in Moore’s Law, heterogeneously integrated chiplet architecture enabled by advanced packaging technologies is becoming essential to enabling the continued economically viable growth of power efficient computing. Decreasing interconnect pitches between the various chiplets, beyond what the conventional solder-based packaging techniques offer, is needed to achieve the required power, performance, area, and cost (PPAC) improvements. We demonstrate hybrid bonding (HB) of stacked chiplets at 9 um bond pitches with die to wafer (D2W) stacking to enable an order of magnitude higher bandwidth between chiplets at lower power and latency compared to existing packaging technologies. Moreover, in the top chiplet, the BPV lands on the top AP instead of the M13 top metal layer, enabling shorter connectivity path. Extensive reliability of these parts in an LGA MCM package has been completed, with the units successfully passing suite of package reliability tests.