Chiplets and Heterogeneous IC Packaging: Building Blocks and Tradeoffs

Chiplets-based IC packages have arrived. This year, many more customers are developing and qualifying their products at Amkor and in the outsourced semiconductor assembly and test (OSAT) and foundry space at large. The rationale for this surge into new multi-die embodiments has been well documented and discussed. In the final analysis, the chiplets approach has become the preferred alternative to large system on chip (SoC) designs. The chiplets approach often permits a better product performance, while lowering total silicon costs. This also enables more transistors in the package than an equivalent SoC, and most importantly, reuse flexibility that reduces time-to-market (TTM) for follow-on products. Heterogeneous IC packages are more expensive than traditional alternatives, for example a single-die Flip Chip ball grid array (FCBGA), but this increase is often offset by lower total silicon cost and the positive time-to-market benefits. However, moving to a heterogeneous approach requires a strong infrastructure to be established for: 1) design, 2) new IC and package structure development and fabrication techniques, and 3) electrical test. IC packaging options to support chiplets have now consolidated into just a few primary constructions that are being developed in the industry and entering early production. These package configurations are much simpler than the now-confusing terminology currently present in the industry. This presentation will review these constructions, simplify their attributes and provide some groundwork for doing the tradeoff analyses during the package construction evaluation and down-selection phase of a project. These higher density integration approaches create modules which integrate the die or chiplets that need ultra fine-line routing for die-die interfaces. Today, these are: (a) modules based on silicon interposers – 2.5D Through Silicon Via (TSV), (b) modules based on High-Density Fan-Out (HDFO) multi-layer redistribution layer (RDL) approaches or (c) modules with bridges. Silicon die can be singular planar devices or combinations using 3D die integration achieved with copper (Cu)-hybrid construction. 1. (c) Bridges (S-Connect) (RDL + Bridge(s)) In Amkor, 2.5D TSV with silicon interposers technology has been in high volume manufacturing (HVM) since 2017. HDFO packaging is internally qualified and currently being qualified for multiple customer products.