Heterogeneous Packaging Technologies for Chiplet and Memory Integration

To meet the High-Performance Computing (HPC) and Artificial Intelligence (AI) market demands of ever higher performance, lower power consumption, wider memory bandwidth with reduced latency, the interconnects connecting D2D in advanced packages are getting ever smaller with tighter bump pitch. Hybrid Copper Bonding (HCB), which can provide direct Cu-Cu connection, is replacing solder-based micro bump Thermal Compressive Bonding (TCB) for die stacking, when the bump pitch shrinks down to less than 20µm. While the interconnects are getting smaller and denser, the overall package size is getting bigger, because more chiplets and High Bandwidth Memory (HBM) need to be assembled on the same package to meet the high-performance requirements. Innovative memory integration solutions, for example memory to logic die 3D stacking, photonic HBM integration, and remote optical HBM connection, are being developed to tackle the issue alternatively. This paper presents a chiplet based heterogeneous integration platform, an advanced custom HBM option, and a menu of advanced packaging offering, which are recently built and delivered by Samsung. including Integrated Stack Capacitor (ISC), Custom HBM, Re-Distribution Layer (RDL) based Fan Out Wafer Level Packaging (FOWLP), Fan Out Panel level packaging (FOPLP), interposer and Si bridge based 2.5 D package architectures, such as I-CubeS, I-CubeR, and I-CubeE, as well as TCB and HCB based 3D IC packaging.