Influence of Mismatched Gate Loop Inductance on Threshold Dispersity Evolution and Current Sharing of Parallel SiC MOSFETs

For high-capacity applications, paralleling multiple silicon carbide (SiC) metal oxide semiconductor field effect transistors (<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s) is essential. However, it is challenging to achieve complete symmetry in the gate circuits of parallel devices, resulting in mismatched gate inductances, which may lead to the current imbalance. This article focuses on investigating the evolution of threshold voltage dispersity under mismatched gate inductances and its impact on the current sharing evolution. It is found that mismatched gate inductances cause the threshold voltage dispersity to increase with gate stress time, thereby inducing a deterioration in current sharing. A boost converter with two devices in parallel was tested, demonstrating that the difference in the minimum turn-off gate voltage including undershoot is the primary trigger for increased threshold voltage dispersity. Besides, an off-state gate voltage optimization strategy was proposed to effectively mitigate the increase in threshold voltage dispersity and improve the evolution of current sharing under mismatched gate loop inductances. The findings are intended to improve the performance of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s in parallel applications.