A 280.580 μm²/Grid, 30.7pJ TMRA-PIM (Time-Multiplexed Random-Access Processing-in-Memory) Programmable Accelerator for Partial Differential Equations Solving and Edge Processing

Hardware accelerators [1–3] employing processing-in-memory (PIM) techniques for solving partial differential equations (PDEs) using finite difference (FD) have received increasing attention thanks to their significant energy efficiency and low latency. However, a trilemma among density, programmability, and low latency hinders the practical use of such an accelerator. The accelerator must compromise its latency and programmability for better density. For instance, in addition to a lack of programmability, prior work in [2] enhances the density of [1] using a processing-near-memory architecture that compromises memory access latency. In contrast, a design in [3] utilized RISC CPU cores as programable processing elements (PEs) with a normalized area overhead $\gt300 \mathrm{x}$ of [2]. In this work, we propose a programmable PDE accelerator capable of both scientific computing and ultra-low power edge processing tasks such as trajectory error correction and pathfinding in robotics applications with minimized area and latency. A test chip with an $11 \times 22$ PE array is fabricated using a TSMC 40nm LP technology. Each PE performs instruction decode and execution via clock throttling, clock gating and data-path reconfiguration. Each executor within PE multiplexes between two memory groups featuring static and dynamic memory, maximizing area efficiency while preserving full functionality for PIM tasks including the ability to operate at a minimum frequency of 0.187 MHz. The test chip occupies a $0.1358 \mathrm{~mm}^{2}$ core area with a density of $280.580~ \mu \mathrm{m}^{2}$ per grid point, consumes $114.97~ \mu \mathrm{W}$ operating at $0.78 \mathrm{~V}, 3 \mathrm{MHz}$, and a 12 -bit computing precision.