A 300-GHz-Band 36-Gb/s Scalable 2x2 2D Phased-Array CMOS Receiver
Two-dimensional beamforming is a significant challenge for subterahertz transceivers. In this paper, we propose a two-dimensional beamforming receiver (RX) circuit that can be expanded to $n \times n$, and report the results of its $2 \times 2$ prototype implemented using 40 nm CMOS technology.
Authors
- Akifumi Kasamatsu (ORCID: https://orcid.org/0000-0002-2217-6272)
- Yoshiki Sugimoto (ORCID: https://orcid.org/0000-0002-3906-3207)
- Shuhei Amakawa (ORCID: https://orcid.org/0000-0002-1596-6604)
- Minoru Fujishima (ORCID: https://orcid.org/0000-0002-6631-0904)
- Satoshi Tanaka (ORCID: https://orcid.org/0000-0002-7101-0690)
- Shunichi Kubo
- Shinsuke Hara (ORCID: https://orcid.org/0000-0002-5183-9725)
- Kunio Sakakibara (ORCID: https://orcid.org/0000-0003-1106-0378)
- Takeshi Yoshida (ORCID: https://orcid.org/0000-0003-3550-0112)
- Kyoya Takano (ORCID: https://orcid.org/0000-0001-7711-3191)
Institutions
- Tokyo University of Science (JP)
- Hiroshima University of Economics (JP)
- Nagoya Institute of Technology (JP)
- National Institute of Information and Communications Technology (JP)
Publication Details
- Published
- 2024-11-18
- DOI
- https://doi.org/10.1109/a-sscc60305.2024.10849080
- Citations
- 5
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 1.04
Funders
- Ministry of Internal Affairs and Communications