Design Optimization of High Voltage Generation for Memristor Electroforming in 28nm CMOS

The process of electroforming (EF) a memristor involves setting the channel resistance via current compliance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{c}\mathrm{c}}$</tex>. This EF phase varies in duration based on the EF voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{EF}}$</tex>, requiring high voltage (HV) as a trade-off with EF time. To achieve CMOS-memristor scalable co-integration, on-chip HV-generation is essential. This study presents an analytical design approach for a proposed three-stage charge pump (CP), focusing on achieving optimal balance among efficiency, output ripple, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{c}\mathrm{c}}$</tex>, and minimal capacitor. The proposed 28 nm three-stage CP requires 1.8 V IO devices for 3.35 V output voltage and achieves 46.5% voltage conversion ratio (VCR). It includes a ripple reduction stage to ensure a ripple below 6mV with high current demands of up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$200 \mu \mathrm{A}$</tex>, without an additional space for over-voltage protection within the CP core. Corners and Monte Carlo simulations are conducted to validate the robustness of the design. By eliminating HV-transistors or multi-phase clocks, the design effectively reduces system costs, enhancing the efficiency and scalability of emerging neuromorphic systems.