A 1.92nJ/Conv Pulse-Width Locked-Loop Time Domain Readout IC with VCO-Integrator and Pipeline TDC for Wheatstone Bridge Wearable Strain Sensing System

The Wheatstone bridge (WhB) is widely used as resistive sensor interfaces, commonly applied in pressure [1], temperature [2], strain [3] sensing systems. Conventional voltage domain WhB (VDWhB) shown in Fig.1(a) requires high performance OTA and large input RCs to reduce power and readout error at the cost of significant area penalty and design complexity. Recently, time domain bridge-to-digital converter (BDC) using a voltage-controlled oscillator (VCO) to convert resistance into frequency has gained significant attention [4] [Fig. 1(b)]. However, the open-loop structure of VCO-based systems limits the gain accuracy and linearity, which can be improved by embedding the VCO in a frequency-locked loop (FLL) based readout [3, 5] [Fig. 1(c)]. Nevertheless, VCO is power-hungry (about 50% of the entire system [3]) as the accumulated jitter has to be suppressed to improve readout accuracy. Additionally, large off-chip capacitors ($\gt10 \mathrm{nF}$) are still required which cannot be readily integrated on-chip [3], [5]. Furthermore, the oversampling time-to-digital converter (OSTDC) adds power overhead while preventing its application from systems with aggressive duty-cycling. To address these issues, we propose a time-domain readout circuit utilizing a VCO-based integrator (VCO-INT) enabled pulse-width locked loop (PWLL) and a Nyquist-rate multi-stage 10-bit pipeline TDC, as illustrated in Fig. 1(d) The overall readout circuit features a digitally-intensive structure with excellent energy efficiency and flexibility.