Analysis and Design of In-Situ Q-Factor Measurement Circuit With Power Reduction

A time-domain Q-factor measurement approach offers the potential of an on-chip Q-factor measurement. To make a step forward towards the final goal, further power reduction of such an implementation system is mandate. This paper delves into a detailed analysis of power consumption of existing circuits, offers an average power consumption model deduced from the analysis made and proposes an improved circuit, which allows greatly further power reduction. The improved circuit was designed in a CMOS <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.35\mu \mathrm{m}$</tex> technology. The simulation results have shown nearly 40% power reduction compared with the previous circuit while still maintaining a wide range of operation frequences from 0.1 to 1.5 MHz and a high Q-factor measurement accuracy of 0.2%.