A 16-30Gb/s 1.03pJ/b Referenceless Baud-Rate CDR with Integrated Pattern Decoding Technique for Fast Frequency Acquisition

Referenceless clock and data recovery (CDR) circuits operate across a range of data rates without an external reference clock. To operate over a range of data rates, several frequency acquisition techniques have been proposed [1–5]. Oversampling CDRs utilize additional clock phases with more than one sample per unit interval (UI), achieving robust frequency acquisition [1–3]. However, due to the additional clock phases, the oversampling CDRs have difficulty in multi-phase clock generation and large power consumption of clock buffers. Compared with the oversampling CDRs, a baud-rate CDR requires one clock phase per UI, reducing the problem from the multi-phase clocking with a reduced number of clock phases. However, previous referenceless CDRs with the baud-rate sampling have increased frequency acquisition time compared to the oversampling CDRs [4–5]. In this work, a referenceless baud-rate CDR with an integrated pattern decoding technique is proposed. While reducing the number of clock phases, the proposed CDR achieves reduced frequency acquisition time by applying weights to divided pattern groups in the integrated pattern decoding logic.