A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM

Increasing amount of data processed by mobile devices and automotive systems has accelerated the rapid growth of mobile DRAM bandwidth. Meanwhile, minimizing a power budget to achieve longer battery life is a critical challenge. A WCK clocking scheme and a low voltage-swing terminated logic (LVSTL) driver are adopted in LPDDR5/5X interfaces to meet these requirements with the strictly limited power budget [1–3]. For further power reduction in a system level, a scenario-based dynamic voltage and frequency scaling core (DVFSC) is also employed to minimize the DRAM power consumption by switching the DRAM supply voltage from VDD2H (1.05V) to VDD2L (0.9V) at low data rates [1].