An LO Double Edge-Tuning IQ Imbalance Calibration Technique for Modern-Day Transceivers

This paper presents an on-chip in phase (I) and quadrature (Q) imbalance technique that improves the error vector magnitude (EVM) and residual side band (RSB) for transmit and receive front-ends. By tuning the delay of the rising and/or falling edge of local oscillator (LO) waveforms, this technique achieves gain adjustment and phase shift correction, effectively negating hardware mismatch without requiring additional circuitry. This novel approach improves the raw residual side band (RSB) before the analog-to-digital converter (ADC), thereby relaxing the signal-to-noise and distortion ratio (SNDR) requirement. The proposed approach is discussed in theory and verified with 180nm CMOS process at 1GHz achieving an EVM floor of better than −73dB with 64QAM modulation corresponding to an image rejection ratio improvement of more than 30dB. When the proposed calibration technique is enabled, the RF front-end's total power consumption varies by less than ±0.15 mW, depending on the calibration code, with an active area that is three orders of magnitude smaller than state-of-the-art solutions.

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Publication Details

Published
2024-11-18
DOI
https://doi.org/10.1109/icecs61496.2024.10848680
Citations
1
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
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An LO Double Edge-Tuning IQ Imbalance Calibration Technique for Modern-Day Transceivers

Hussam AlShammary
1 citations
Radio Frequency Integrated Circuit Design
0.21
article

An LO Double Edge-Tuning IQ Imbalance Calibration Technique for Modern-Day Transceivers

Hussam AlShammary
article en
1 citations

Abstract

This paper presents an on-chip in phase (I) and quadrature (Q) imbalance technique that improves the error vector magnitude (EVM) and residual side band (RSB) for transmit and receive front-ends. By tuning the delay of the rising and/or falling edge of local oscillator (LO) waveforms, this technique achieves gain adjustment and phase shift correction, effectively negating hardware mismatch without requiring additional circuitry. This novel approach improves the raw residual side band (RSB) before the analog-to-digital converter (ADC), thereby relaxing the signal-to-noise and distortion ratio (SNDR) requirement. The proposed approach is discussed in theory and verified with 180nm CMOS process at 1GHz achieving an EVM floor of better than −73dB with 64QAM modulation corresponding to an image rejection ratio improvement of more than 30dB. When the proposed calibration technique is enabled, the RF front-end's total power consumption varies by less than ±0.15 mW, depending on the calibration code, with an active area that is three orders of magnitude smaller than state-of-the-art solutions.

Openalex Percentile: Top 44%
Radio Frequency Integrated Circuit Design
0.21
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