Design and Benchmark of Iso-Area High Cell Current 5T Asymmetric (5TA) SRAM Cell with Up to 10X Lower Leakage

Embedded memories occupy up to 70% of the area and account for 30-50% of power consumption in advanced digital SoCs. A large part of this power is leakage power. Therefore, low-leakage SRAM cells are desirable. We propose an iso area asymmetrical 5TA SRAM cell and benchmark it with conventional 6T, 5T, and 4 T SRAM cells. Our analysis shows that the proposed 5TA cell has about 10X and 6.23X lower leakage than the conventional SRAM cell in 130n<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$m$</tex> and 65nm CMOS technology, respectively at a similar performance point.