Utilization of TST-MRAM in a Hyperdimensional Associative Memory

This paper presents the integration of toggle spin torque random access memory (TST-MRAM) in the associative memory (AM) for a more energy-efficient hyperdimensional computing (HDC) architecture. The proposed AM is composed of a TST-MRAM array connected to loser-takes-all comparators, which function together as memory and classifier. The model exploits the differences in capacitor discharge times for the different classes in determining the most similar class. We implement the TST-MRAM-based AM in GlobalFoundries 22 nm FD-SOI technology, with language classification as the target application. Our results show that the proposed model performs a single query faster than the conventional CMOS-based AM. However, it is less energy-efficient due to the inherently low ON/OFF resistance ratio of TST-MRAM cells, resulting in a 7.75x reduction in energy-delay product. Despite this, we project that the proposed model is able to outperform the conventional CMOS-based AM when memory cells with higher inherent resistances are developed.